Type of Timing Analysis
Timing analysis can be verified by two methods
- Dynamic Timing Analysis (DTA)
- Dynamic timing analysis includes both functional and timing analysis of design. Hence it is timing consuming.
- Ideally possible only for small designs
- Requires SPICE models & Vectors to verify/do timing analysis.
- DTA analysis saws results only for paths which are part of vector or being excersied only if its part of vector. Hence there is possibility of missing few paths if not covered in Vector or incorrect/incomplete vector.
- Static Timing Analysis:
- STA is method of validating timing performance of Circuit by checking all possible timing paths.
- In this static timing analysis large gate level Netlist is checked without Vector approach.
- Assumptions should be circuit is functional.
- STA considers each and every timing path, might result into false timing violation results, In practise we can add exceptions to design to mask these kind of false paths.
- Delay in Circuits:
- Delay is being calculated based on signal propagate from one point to another part of circuit.
- Two types of delay are there in timing analysis.
- Cell delay, Propagation dealy (Signal to propagate through gates)
- Wire delay/Net delay /Interconnect delay
- Transition delay or Slew is time taken by signal to change its state i.e from 1 to 0, 0 to 1.
- Understanding of Timing analysis Concepts
- Set-up Time
- Setup time is time interval before clock's active clock edge Data should remain stable otherwise it may lead flop to go in metastable state.
- Hold Time
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