Special Retention Register: Zero Pin Register(ZPR)

• Zero Pin Retention Register
• Zero pin retention is a standard retention cell, except it has no save/restore pins. During retention, clock must be clamped low and reset must be clamped high with always on signal. Zero pin retention cells must have below mentioned Cell level liberty attribute.
  
  
  
  1. Clamp gates (Isolation cells) are associating with retention strategy and do not have isolation strategies.
  2. Isolation cells placed before CLK and NRST pin should have same sense value, then only zero-pin retention cell works correctly.
     
     
  • Consider above figure for save/restore functionality of zero-pin retention cell:
    1. When RETAIN signal value is 1,
    • CLK pin is clamped to low and NRST pin is clamped to high and zero-pin retention cell retains the value. 
    2. When RETAIN signal value is 0,
    • Zero-pin retention cell restores the retained value and work as normal flip-flop.  
    3. When RETAIN signal value is 0 and value at NRST pin is 0, 
    • Zero-pin retention cell is in reset state.