Scripting Magic

1. Random Number generation using Make file:

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          RANDOM := $(shell /bin/bash -c "echo $$RANDOM")

          test:
                         echo $(RANDOM)
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Linux type below:
> make test
echo 5184

5184

         

IR Drop

• IR Drop is related to voltage drop in power distribution interconnects in a chip which can be static or dynamic or both. This drop can reduce supply voltage reaching to the standard cell. So standard cell may not work perfectly.
• Static IR Drop:
• Static IR drop are drop in VDD voltage level caused by resistance of wire metal used in power distribution.
• In other words it is the drop due to current flow through the interconnects wires when circuit is at steady state. e.g. no inputs are switching.
• The factor affecting the static IR drop are basically the dimension of power rails, width, via, power switch sizes etc..
• Dynamic IR Drop:
• Dynamic IR drop refers to the voltage drop in VDD due

Floor Planning

• Introduction To Floor Planning
• This is the first major step in getting your layout done, and this is the most important one.Your floor plan determines your chip quality. Floor planning includes.

1. Define the size of your chip/block and Aspect ratio
2. Defining the core area and IO core spacing
3. Defining ports specified by top level engineer.
4. Design a Floor Plan and Power Network with horizontal metal layer such that the total IR Drop must be less than 5% (VDD+VSS) of VDD to operate within the power budget.
5. IO Placement/Pin placement
6. Allocates power routing resources
7. Place the hard macros (fly-line analysis) and reserve space for standard cells. (Please refer rules for placing hard macros)
8. Defining Placement and Routing blockages blockages
9. If we have multi height cells in the reference library separate placement rows have to be provided for two different unit tiles.
10. Creating I/O Rings
11. Creating the Pad Ring for the Chip
12. Creating I/O Pin Rings for Blocks

• Floor planning takes in some of the geometrical constraints in a design. Examples of this are:
• Bonding pads for off-chip connections (often using wire bonding) are normally located at the circumference of the chip.
• Line drivers often have to be located as close to bonding pads as possible.
• Chip area is therefore in some cases given a minimum area in order to fit in the required number of pads.
• Areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel sifter, line driver and arithmetic logic unit.
• Purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks.
• Some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.
• Inputs for Floor Planning Stage:
• Synthesized Netlist (.v, .vhdl)TLU+ Files
• Physical partitioning information of the design
• Design Constrains (SDC)
• Physical information of your design (rules for targeted technology)
• Floorplan parameters like height, width, utilization, aspect ratio etc.
• Pin/pad Position
• Logical and Physical Libraries
• Outputs for Floor Planning Stage:
• Die/Block area
• Macro placed
• Power grid design
• Power pre-routing
• Standard cell placement areas.
• I/O pad/placed

Basic things to know about ASIC VLSI Back-end

• Required tools sets for VLSI Back-end.
• Synthesis:
• Design Compile
• Fusion compile
• RTL Compiler
• DFT (Design For Test)
• DFT Max
• RTL Compiler
• Floor Planning
• Jupiter-XT
• SOC-Encounter-Nano Place
• Innovus 
• Partitioning
• Jupiter-XT
• SOC-Encounter-First Encounter
• Innovus 
• Power Planning
• Jupiter-XT, Primetime
• SOC-Encounter-First Encounter
• Innovus 
• ICC2/Fusion compile 
• Placement
• Jupiter-XT, Astro
• SOC-Encounter-First Encounter
• ICC2/Fusion compile 
•  Clock Tree Synthesis
• Jupiter-XT
• SOC-Encounter-First Encounter
• ICC2/Fusion compile 
• Routing
• Jupiter-XT
• SOC-Encounter-Nano Place
• ICC2/Fusion compile 
• Power Verification (Out GDS-II)
•  Herculis
• Assura
• ICC2/Fusion compile 

Physical Design Flow with i/o+ tools

 

Synthesis & Optimization

1. RTL goes through optimization 

Special Retention Register: Zero Pin Register(ZPR)

• Zero Pin Retention Register
• Zero pin retention is a standard retention cell, except it has no save/restore pins. During retention, clock must be clamped low and reset must be clamped high with always on signal. Zero pin retention cells must have below mentioned Cell level liberty attribute.
  
  
  
  1. Clamp gates (Isolation cells) are associating with retention strategy and do not have isolation strategies.
  2. Isolation cells placed before CLK and NRST pin should have same sense value, then only zero-pin retention cell works correctly.
     
     
  • Consider above figure for save/restore functionality of zero-pin retention cell:
    1. When RETAIN signal value is 1,
    • CLK pin is clamped to low and NRST pin is clamped to high and zero-pin retention cell retains the value. 
    2. When RETAIN signal value is 0,
    • Zero-pin retention cell restores the retained value and work as normal flip-flop.  
    3. When RETAIN signal value is 0 and value at NRST pin is 0, 
    • Zero-pin retention cell is in reset state.