Floor Planning

• Introduction To Floor Planning
• This is the first major step in getting your layout done, and this is the most important one.Your floor plan determines your chip quality. Floor planning includes.

1. Define the size of your chip/block and Aspect ratio
2. Defining the core area and IO core spacing
3. Defining ports specified by top level engineer.
4. Design a Floor Plan and Power Network with horizontal metal layer such that the total IR Drop must be less than 5% (VDD+VSS) of VDD to operate within the power budget.
5. IO Placement/Pin placement
6. Allocates power routing resources
7. Place the hard macros (fly-line analysis) and reserve space for standard cells. (Please refer rules for placing hard macros)
8. Defining Placement and Routing blockages blockages
9. If we have multi height cells in the reference library separate placement rows have to be provided for two different unit tiles.
10. Creating I/O Rings
11. Creating the Pad Ring for the Chip
12. Creating I/O Pin Rings for Blocks

• Floor planning takes in some of the geometrical constraints in a design. Examples of this are:
• Bonding pads for off-chip connections (often using wire bonding) are normally located at the circumference of the chip.
• Line drivers often have to be located as close to bonding pads as possible.
• Chip area is therefore in some cases given a minimum area in order to fit in the required number of pads.
• Areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel sifter, line driver and arithmetic logic unit.
• Purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks.
• Some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.
• Inputs for Floor Planning Stage:
• Synthesized Netlist (.v, .vhdl)TLU+ Files
• Physical partitioning information of the design
• Design Constrains (SDC)
• Physical information of your design (rules for targeted technology)
• Floorplan parameters like height, width, utilization, aspect ratio etc.
• Pin/pad Position
• Logical and Physical Libraries
• Outputs for Floor Planning Stage:
• Die/Block area
• Macro placed
• Power grid design
• Power pre-routing
• Standard cell placement areas.
• I/O pad/placed